1. Field
Various features relate to digital circuits, and in particular to devices and methods for reducing noise in digitally controlled oscillators.
2. Background
An all-digital phase locked loop (PLL) is a digital control system that generates an output signal whose phase is related to the phase of an input “reference” signal. A PLL is an electronic circuit comprising a digitally controlled, variable frequency oscillator (DCO) and a phase detector. The PLL compares the phase of the input signal with the phase of the signal derived from its output DCO and adjusts the frequency of its DCO to keep the phases matched. The signal from the phase detector is used to control the DCO in a feedback loop.
A DCO operates by receiving a digital input signal level (e.g., a multi-bit control word) as an input and generating an output signal having a frequency corresponding to the input signal level. A typical DCO may utilize an LC-tank having a variable capacitor that can be tuned in order to adjust its resonant output frequency. Thus, the input signal level (e.g., control word) in effect controls controls the output frequency of the DCO by adjusting the capacitance value of the variable capacitor.
The variable capacitor used in a typical DCO may include a plurality of capacitor banks where each capacitor bank includes a plurality of individual capacitors. These individual capacitors may be independently enabled so that their capacitance value is contributed to the total capacitance of the DCO's LC tank. As one example, a variable capacitor of a DCO may comprise two distinct capacitor banks A and B that are coupled to each other in parallel. Capacitor bank A includes three distinct capacitors CA1, CA2, CA3 coupled in parallel that each have equal capacitance values. Capacitor bank B includes seven capacitors CB1, CB2, CB3, CB4, CB5, CB6, CB7 that are also coupled in parallel and also each have equal capacitance values. The capacitance value of each bank A capacitor CA is equal to eight times that of the capacitance value CB of the capacitors in bank B. Thus, CA=8*CB.
The DCO receives control words that enable or disable the aforementioned capacitors CA1, CA2, CA3, CB1, CB2, CB3, CB4, CB5, CB6, CB7 in order to generate a corresponding output frequency. For example, a binary control word “00111” may enable capacitors CB1, CB2, CB3, CB4, CB5, CB6, CB7 for a total capacitance value of 7*CB, whereas the control word “01000” may enable capacitor CA1 for a total capacitance value of 8*CB (since CA=8*CB).
Notably, when the control word transitions from “00111” to “01000” seven capacitors CB1, CB2, CB3, CB4, CB5, CB6, CB7 from capacitor bank B are disabled (i.e., decoupled from the LC-tank output) and one large capacitor CA1 from capacitor bank A is enabled (i.e., coupled to the LC-tank output). Such points of transition where multiple capacitors are coupled and decoupled at once from multiple banks for the DCO output frequency to increment/decrement one step are herein referred to as “capacitor bank sensitive boundaries,” and the control words that are adjacent to such boundaries are referred to as “boundary-sensitive control words.”
FIG. 1 illustrates an example of such capacitor bank sensitive boundaries and control words and the effect they have on the total output variable capacitance CVar of a DCO found in the prior art. A table 100 depicts a portion of the plurality of 5-bit control words that may control the output frequency of the DCO. The first two most significant bits (MSBs) of the control word in this example control (i.e., enable/disable) the aforementioned bank A capacitors and the three least significant bits (LSBs) control the bank B capacitors. The table shows four (4) boundary-sensitive control words (the control words having the hatched background) and two (2) capacitor bank sensitive boundaries 102a, 102b that each separate the pairs of boundary-sensitive control words.
In the illustrated example, a DCO input control word signal is undergoing a small oscillation between the two boundary-sensitive control words “00111” and “01000.” As a result, the output variable capacitance CVar also oscillates back and forth between CA1 and CB1+CB2+CB3+CB4+CB5+CB6+CB7. Thus, many capacitors across a plurality of different capacitor banks are being enabled and disabled at the same time as the input control word transitions between the boundary-sensitive control words. Specifically, the example shown one (1) larger capacitor from bank A is enabled (i.e., coupled to the output) and seven (7) smaller capacitors from bank B are disabled (i.e., disconnected from the output).
Coupling and decoupling so many capacitors from different capacitor banks at the output of the DCO injects noise into the DCO output signal. Moreover, inherent mismatches among the different capacitor banks (e.g., capacitor banks A and B) contribute noise and/or frequency inaccuracies to the DCO output signal when switching between capacitor banks at capacitor bank sensitive boundaries. Although individual capacitors within a single capacitor bank may be relatively well matched with one another, capacitors from different banks may not be so well matched. For instance, in the example discussed above it was assumed that each capacitor from bank A has a capacitance value CA that is equal to eight (8) capacitors CB from bank B. In practice, however, manufacturing variability may cause CA1 to be, for example, greater than 8*CB and capacitors CB1+CB2+CB3+CB4+CB5+CB6+CB7 together to be less than 7*CB. This deviation from the expected step increment may be expressed as Cerror as shown in FIG. 1, and may be relatively large due to the greater mismatch between different capacitor banks.
As one example, manufacturing limitations may result in a bank A capacitor CA to equal 8.3*CB (instead of 8*CB) and capacitors CB1+CB2+CB3+CB4+CB5+CB6+CB7 together may equal 6.9*CB (instead of 7*CB), resulting in a capacitance deviation of Cerror=0.4*CB. Thus, transitioning from control word “00111” to “01000” would cause the output variable capacitance to transition from 6.9*CB to 8.3*CB instead of from 7*CB to 8*CB. Such a significant deviation from the desired capacitance step change results in increased DCO output noise.
Noise caused by such transitions at capacitor bank sensitive boundaries may cause significant problems for PLLs employing DCO's using such variable capacitors. In particular, these problems become much more pronounced when the PLL settles at an output frequency near one of the capacitor bank sensitive boundaries. Settling at such a point may cause the capacitor banks to repeatedly and/or periodically enable and disable many capacitors across two or more capacitor banks as the control word controlling the DCO transitions back and forth between boundary-sensitive control words (e.g., 00111 and 01000). This may cause persistent noise injection problems and nonlinearities.
Thus, there exists a need to improve noise performance of DCOs utilizing variable capacitors comprising a plurality of capacitor banks. In particular, there exists a need to reduce noise injected by the variable capacitor at capacitor bank sensitive boundaries. Reducing such noise would improve the performance of the DCO and any circuits relying on the DCO, such as a PLL, for a linear, low-noise output frequency signal.